A substrate for an integrated circuit (IC) package or an IC package substrate is an intermediate substrate electrically connecting a semiconductor chip to a printed circuit board (PCB), acting as an interface to transfer electrical signals between semiconductor chips and the PCB. At this time, solder bumps are generally used to electrically connect the semiconductor chip to the IC package substrate. Such a connection process is referred to as a reflow process. The reflow process is undertaken at about 260° C. for about 20 seconds, followed by a process of cooling to room temperature. However, when cooled to room temperature, the IC package substrate may have a warping defect, due to a difference in coefficients of thermal expansion (CTEs) between the upper semiconductor chip and the lower IC package substrate. That is, the CTE of Si, mainly used as a semiconductor chip material, is about 2.6 ppm/° C., while the CTE of a copper clad laminate (CCL), conventionally used as an IC package substrate, is about 15 ppm/° C. Such a significant CTE mismatch between the upper semiconductor chip and the lower CCL causes non-coincidental thermal expansion between the two layers in a high temperature reflow process performed at 260° C. Thus, during the cooling process, the two layers may have a warping defect instead of maintaining the original shapes thereof being maintained. In addition, when a warping defect occurs, the solder bumps electrically connecting the two layers may be broken, thereby causing electrical disconnection, i.e. a failure in the transmission of an electrical signal. Here, in the case of a substrate having a certain thickness, a significant defect is not caused by the CTE difference. However, since the thickness of the substrate may be reduced in accordance with the current trend within the semiconductor industry for lighter, thinner, and smaller designs, a CTE difference is more likely to cause a warping defect and a variety of resultant defects, with decreases in the thickness of the substrate. In addition, in accordance with the trend within the semiconductor industry for lighter, thinner, and smaller designs, the thickness of the semiconductor chip is being further reduced along with a smaller pitch size. As described above, the size of micro solder bumps also decreases with decreases in the pitch size. In this case, the micro solder bumps may be more vulnerable to a warping defect, i.e. may be broken even by a small warping defect.
[Related Art Document]
Patent Document 1: Korean Patent No. 10-0648968 (Nov. 16, 2006)